1. Field of the Invention
The present invention relates to an optical disk reproducing apparatus for locking-in a phase lock loop for reproducing a clock more easily by controlling the phase lock loop or a waveform equalizer by detecting a linear velocity period from a reproduced signal digitally recorded on an optical disk medium.
2. Description of the Related Art
In order to make full use of the capacity of a recording medium most effectively, a recording method for unifying the recording density on the recording medium by setting a linear velocity to be constant is frequently used, for example, in a compact disk. In the case where a phase lock-in is performed with respect to an optical disk reproduced signal which has been digitally modulated and recorded after performing a mark width modulation so that the linear recording density becomes constant, a pseudo lock-in is very likely to be performed unintentionally. That is to say, the lock-in is likely to result in a frequency different from the clock frequency of the reproduced signal, unless the lock-in is started in a state where the frequency of a clock component of the reproduced signal is proximate to the frequency of a clock generator of a phase lock loop circuit. In order to avoid such a pseudo lock-in, the reproducing linear velocity of the optical disk and a pulse width or a pulse interval contained in a modulated signal are detected, thereby controlling the rotation speed of the disk and the free-run frequency of the phase lock loop and enabling a normal phase locking pull-in.
Such a phase lock-in is realized, for example, by a disk reproducing system shown in FIG. 16. Data such as the data shown in FIG. 17A is recorded on an optical disk 28 so that the linear recording density becomes constant. In this case, the recorded data is assumed to be data regulated so that the number of successive "0" or "1" is in a range from 3 to 11. That is to say, an eight to fourteen modulation (EFM), for example, is employed as a modulation method. A reproduced signal reproduced by a reproducing section 29 exhibits a low-pass filtering characteristic, and therefore, the amplitude of the signal component decreases as the frequency thereof becomes higher. In order to correct the decrease in the amplitude, a high-frequency band is boosted by a waveform equalizing section 1. A treble-boosted reproduced signal (FIG. 17B) is digitized at a predetermined slice level by a digitizing section 2 so as to convert the signal into a digitized signal (FIG. 17C). In this case, an optimum value of the slice level is variable depending upon the variation of the size of a recording mark or the like, but can be automatically adjusted in accordance with the DC component of the reproduced signal.
When a digitized signal is input, a phase comparator 22 compares the phase of the input signal with the phase of the output from a voltage control oscillator 21, thereby generating a phase error voltage corresponding to the phase difference therebetween. A charge pump 23 discharges or absorbs a constant current in accordance with the phase error voltage. A loop filter 24 converts the current output from the charge pump 23 into a voltage, and simultaneously limits the bandwidth thereof. Then, the voltage control oscillator 21 varies its output clock frequency in accordance with the output voltage from the loop filter 24, thereby a phase lock loop is formed. The phase lock loop generates a clock signal (FIG. 17D), the phase of which is synchronized with that of the clock component of the input digitized signal (FIG. 17C). Thereafter, a synchronizing section 6 synchronizes the digitized signal (FIG. 17C) with the synchronized clock signal (FIG. 17D), thereby outputting the synchronized clock signal and the digitized signal data synchronized with the synchronized clock signal.
However, the possibility of a pseudo lock-in cannot be eliminated only by the phase lock loop described above, especially in the situation where the free-run frequency of the voltage control oscillator 21 is much different from the clock frequency of the input digitized signal when the phase lock-in is started. In general, the phase lock-in can be performed so long as the difference between the free-run frequency of the voltage control oscillator 21 and the clock frequency of the digitized signal is within .+-.5%. Once the difference exceeds this value, an abnormal pull-in is possibly performed. Therefore, an 11T period detecting section 25 is further provided as a first auxiliary lock-in section in addition to the phase lock loop for measuring the temporal period of the recording pattern of the digitized signal (FIG. 17C) where "0" or "1" successively appears 11 times. A predetermined amount of current is injected or absorbed from the charge pump into the loop filter so that the oscillation frequency of the voltage control oscillator becomes low if the measured value is longer than the steady-state value, or that the oscillation frequency of the voltage control oscillator 21 becomes higher if the measured value is shorter than the steady-state value. Phase lock-in can be performed without causing a pseudo lock-in by performing this operation until the oscillation frequency of the voltage control oscillator becomes substantially equal to the frequency of the clock component of the digitized signal.
In addition, by providing a 6T period detecting section 26 as a second auxiliary lock-in section, the temporal period of the recording pattern (000111) or (111000) existing in the digitized signal (FIG. 17C) is measured. If the measured value is larger than the steady-state value, the rotation speed of the motor is accelerated. Alternatively, if the former is shorter than the latter, the rotation speed of the motor is decelerated so as to be proximate to a steady-state linear velocity, whereby making the frequency of the clock component of the digitized signal substantially equal to the free-run oscillation frequency of the voltage control oscillator. Thus pseudo lock-in is eliminated. In this case, the period of the recording pattern (000111) or (111000) corresponds to the period of a rising interval or a falling interval of the digitized signal. Even when a digitizing slice level is varied in the digitizing section 2, such a variation hardly affects the detection period. Therefore, it is possible to realize a detection which is highly resistant to some disturbance for a retrieval seek operation or the like. On the other hand, the 11T period detecting section 25, functioning as a first auxiliary pulling-in section, detects a period from a rising to a falling or a period from a falling to a rising. Therefore, if the digitizing level is varied, then the 11T period detecting section 25 cannot perform a normal detection any longer. Nevertheless, since the period to be detected by the 11T detecting section is long, the precision of the detection is not degraded so much.
In the situation where information recorded on an optical disk medium is retrieved at a high speed for reproducing data therefrom, it is required to perform a phase lock-in at a high speed with respect to a reproduced signal from the disk.
However, according to a method, such as the 6T period detection described above, in which the period of the linear velocity for the optical disk is detected for controlling the rotation speed of the disk, it takes a long time until the rotation speed is settled, so that a considerable amount of time is required before starting the phase lock-in for reproducing a clock. On the other hand, according to a method, such as the 11T period detection described above, in which the pulse width or the pulse interval contained in the modulated signal is detected and the level thereof is compared with that of the steady-state value and a predetermined amount of current is injected or absorbed from the charge pump into the loop filter for controlling the free-run frequency of the voltage control oscillator, the precision of the control is not satisfactory because the control is a digital control. That is to say, there is not any way other than raising or lowering the frequency.